A constant goal for the semiconductor industry is to continuously reduce the operating voltage and power required in semiconductor devices. The present invention is directed toward achieving this goal in SRAM arrays.
SRAM or other conventional memory devices are typically included in electronic systems for data storage. These memory devices store data in arrays of memory cells. Each cell conventionally stores a single bit of data (either a “1” or a “0”) and can be individually accessed or addressed. Data is output from a memory cell during a READ operation, and data is stored into a memory cell during a WRITE operation.
In a READ or WRITE operation, a column decoder and a row decoder translate address signals into a single intersection of a row or word-line and column or bit-line within the memory array. This function permits the memory cell at that location to READ data from or WRITE data to the memory cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells.
FIG. 1 is an exemplary block diagram of a background art SRAM subarray with a sense amplifier. In particular, FIG. 1 shows signals RBS0 and RBS1 control the selection of one of two columns that share sense-amplifier circuitry. FIG. 1 also shows the signal BLR, which controls the Bit-line BL pre-charge PFETs T0, T2, T3, T4 that are normally unselected during the READ or WRITE operations.
Further, FIG. 1 shows the signal SUBSEL which enables the selected subarray that share global bit-line signals GBLT, GBLC signals with other subarrays. The SUBSEL signal transitions to VDD for the selected subarray. Unselected subarrays have their own unique SUBSEL signals at ground GND.
Further, in the background art schematic diagram shown in FIG. 1, selected columns have their bit-lines BLT0, BLC0 or BLT1, BLC1 coupled to the data lines DLC, DLT through selected bit switch devices T5-T8 and T12-T15. The columns selected by SUBSEL will see full signal amplification when the sense-amplifier circuit is enabled. However, in the background art, the unselected columns (i.e., half-selected column) do not see full bit-line amplification, and the internal SRAM cell node (i.e., NC or NT, as shown in FIG. 2 and further discussed below) is not quickly discharged to GND. These conditions limit the operating voltage of SRAM arrays.
To improve the stability margin of the SRAM cell and increase the operating margin, Sense Amplifier Assist (SAA) circuitry is added to the SRAM array. SAA features the addition of sense-amplifiers on every SRAM column to quickly discharge bit-lines during READ and unselected-WRITE operations (i.e., on half-selected columns). In general, adding SAA circuitry enables a wider operating voltage range for semiconductor devices. However, when a sense-amplifier is set on every bit-line in a subarray during READ and WRITE operations, every true or complement bit-line in the selected subarray transitions from VDD to ground GND and back to VDD during pre-charge. This mode of operation is a problem for the background art using SAA circuitry with SRAM architectures due to the power consumption penalty associated with these voltage transitions.
In some background art embedded applications, the additional power consumption that results from the above-discussed voltage transitions on the bit-lines is intolerable and thus, SAA cannot be implemented. However, without SAA, the SRAM may have a problem with meeting the voltage requirements of low power embedded applications.
FIG. 2 shows a memory cell of a background art SRAM. In particular, the memory cell of FIG. 2 includes a pair of cross-coupled inverters that together form a latch that retains the voltage levels on a pair of complimentary bit nodes BLC and BLT. A first access transistor extends between bit-line BLT and bit node NT, and a second access transistor extends between complimentary bit-line BLC and memory bit node NC.
To effect a WRITE operation for the memory cell in FIG. 2, the data to be written to the memory cell is driven onto complimentary bit-lines BLC and BLT and word line WL is asserted (e.g., driven high) to render the access transistors conducting. The respective voltages on bit-lines BLC and BLT are thereby conveyed to cross-coupled inverters. The word line signal WL is then de-asserted, disconnecting the complimentary bit-lines BLT, BLC from their respective bit nodes NT, NC. The cross-coupled inverters thereafter retain a voltage level representative of the written bit.
To effect a READ operation for the memory cell shown in FIG. 2, bit-lines BLC and BLT are pre-charged to some known level, typically to supply voltage VDD. Word line signal WL is then asserted, so that cross-coupled inverters drive the latched voltage level onto complimentary bit-lines BLC and BLT. A sense amplifier detects the resulting logic level on the bit-lines.
However, yet another problem exists with this background art circuit configuration. During a read cycle, as the bit-lines BLC, BLT are discharged by the cell, the internal voltage on the cell nodes NC, NT can rise to a level that can reach the switch point of the cross-coupled inverter of the cell. This rise in voltage level on the internal nodes can disturb or distort the SRAM data.
FIG. 3 shows exemplary waveforms from the background art SRAM cell of FIG. 2. As shown in FIG. 3, the voltage level of the internal nodes NT, NC of FIG. 2 rise due to the affects of feedback in the cross-coupled inverter of the memory cell. This rise in voltage level results in the voltage levels on internal nodes NC, NT dropping from VDD. Substantial variations in the voltage levels of the internal nodes NC, NT can eventually flip or disturb the state of the cell causing additional problems with this background art circuit configuration.
FIG. 4 is an exemplary graph illustrating the SRAM cell stability margins with technology migration/scaling to obtain smaller feature sizes. Increasing variations in threshold voltage (Vt) with technology scaling decreases the operating margin and stability ratios between the rising internal voltages on the cell nodes NC, NT and the switch-point of the cross-coupled inverter. This is indicated in FIG. 4 by the vanishing space between the cell switch-point and the read down level as feature size is reduced.
In addition, the discharge rate of the bit-line, as it is read, has a strong influence on the stability margin of the cell. For example, in long, heavily-loaded bit-lines, the voltage between the cell node and the inverter switch-point remains very small for a relatively long period as the bit-line is slowly discharged. Thus, long, heavily-loaded bit-lines are more sensitive to Vt variations and therefore will have a smaller operating voltage range. Conversely, short, lightly-loaded bit-lines are quickly discharged by the cell, which in turn, rapidly discharges the cell node voltages to GND or VSS.
In an attempt at improving the stability margin of a semiconductor cell and increase the operating margin, background art SRAM array designs have implemented short bit-line architectures. However, a problem with these short bit-line architectures is that they are not an effective means for improving stability in low-power technologies where the SRAM READ currents are very small. In particular, the number of SRAM cells on a bit-line would have to be in the range of 16 to 32 SRAM cells in order to observe a significant improvement in either stability or operating margin with the short bit-line architecture approach. Further, the SRAM array efficiency with short bit-line architectures is so poor that this method is often an unacceptable solution even in higher power embedded applications.
Therefore, it is clear that there is a need in the art for improvements in the performance of SRAM circuit architectures with SAA, particularly in low power applications.